1, responsible for the improvement of the financial system and the implementation of the company’s financial and tax work to guide the implementation of the company’s leadership in a timely manner to make financial reporting and make practical advice and financial guidance;
2, responsible for the cost of the company, the cost of sales and profit accounting, the provision of various types of taxes payable for tax;
2, regularly check the current accounts, timely liquidation receivable payable;
3, the completion of the preparation of accounting documents, audit, accounting and reporting of relevant financial reports and statements, truthfully reflect the company’s financial activities,
To complete the formalities, the content is true, accurate data, clear accounts, scheduled to report;
1, college degree or above, major in finance or accounting;
2, financial supervisor work experience is preferred;
3, familiar with the accounting statements, accounting regulations and tax laws, skilled use of financial software;
4, good learning ability, independent working ability and financial analysis ability;
5, work carefully, strong sense of responsibility, good communication skills, team spirit.
1, according to system requirements, the design of the system FPGA program;
2, responsible for the overall design of the FPGA program, module division, the key modules of the logic design, simulation, debugging;
3, determine the principle of the design of the FPGA program, to assist in the schematic design of the relevant FPGA;
4, with the hardware and software designers to complete the relevant mission objectives;
5, the preparation of FPGA design documents, test documents and the use of documents, etc..
1, bachelor degree or above, major in communication, electronics, more than three years working experience;
2, familiar with the FPGA program architecture design, digital intermediate frequency DDC/DUC RTL level design, algorithm implementation, etc.;
3, familiar with the IR protocol, CPRI protocol, the design of high speed AD/DA interface design, familiar with Gigabit Ethernet / Fast Ethernet RTL design, familiar with various types of digital repeater, RRU, multimode system development design;
4, the application of high-speed Serdes (10Gbps), cross clock domain processing, reduce resources, improve clock performance and timing optimization has some research and experience;
5, master xlinx FPGA chip features and VIVADO development environment, proficient in Verilog coding;
6. Good team player and team management skills;
7, project team experience is preferred.
1, the daily laboratory system testing and hardware and software version maintenance / control;
2, system level test case design, maintenance and product continuous optimization test;
3, build and maintain system automation test platform to achieve product quality control;
4, the organization and coordination of field test work;
5, field test execution and test data / test report;
4, hands-on ability, familiar with the field of communication system installation and commissioning.